The present invention relates generally to chips having partitioned logic and, more particularly, to masking, such as lithographic masking, in connection therewith.
As silicon capability continues to double every 18 months, the ability to design and manufacture chips increasingly becomes key to their deployment. The times required to synthesize chips have begun to exceed the required time to market. The increasingly complex efforts relating to physical design of the chips have accorded a great sense of urgency on handling xe2x80x9csecond orderxe2x80x9d effects to meet time-related goals. For instance, the resolution of minimum device features comparable to (or smaller than) the wavelength of the exposing light has made the lithography for mask making increasingly complex and expensive. All of these second order effects are conspiring to increase the cost of designing a chip to the point where only high volume chips are economically viable.
The industry has responded to this situation by initiating the development of System-On-a-Chip (SOC) methodologies. This approach is successful in partitioning the logic on a chip into quasi-independent regions. However, the difficulty in practicing SOC has led to the introduction of a xe2x80x9cplatformxe2x80x9d approach, wherein variants within the class of designs are implemented on identical or nearly identical hardware.
This platform approach leaves some of the customization of the SOC to software, which, from the point of view of productivity, appears to present even greater problems than hardware. The SOC approach fails to address the dramatically increasing costs related to mask data preparation and mask building. Though methods involving partitioning and hierarchy have been helpful in the synthesis and design of both chips and systems, the SOC approach does not use such methods for the mask generation process.
In view of the foregoing, a need has been recognized in connection with decreasing the time-to-market associated with chip manufacture, addressing the problem of dramatically increasing data generation and mask build costs, and providing an expanded model for sharing the masks of significant portions of a chip.
In accordance with at least one presently preferred embodiment of the present invention, a partitioned mask layout approach is broadly contemplated. As will be appreciated from the detailed discussion herebelow, this approach provides the chip exposure pattern as a set of partitions corresponding to macros or core functions and also handles glue logic and interconnect. A result of this approach is a simplified, cost-effective process that does not defer customization to other, potentially more time-consuming and inefficient tasks. It will be appreciated that the sharing of masks or mask data to dramatically decreases both time to market and the non-recurring-engineering (NRE) cost of chip design.
In one aspect, the present invention provides a method of providing masking for a chip having partitioned logic, the method comprising the steps of: providing a chip having partitioned logic; providing masking; the step of providing masking comprising providing a chip exposure pattern, the chip exposure pattern comprising at least one partition corresponding to at least one of: at least one macro of the chip and at least one core function of the chip.
In an additional aspect, the present invention provides masking for a chip having partitioned logic, the masking comprising a chip exposure pattern, the chip exposure pattern comprising at least one partition corresponding to at least one of at least one macro of the chip and at least one core function of the chip.
For a better understanding of the present invention, together with other and further features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, and the scope of the invention will be pointed out in the appended claims.